The present invention relates to a memory device and, particularly, to a memory device including a common source line that commonly connects sources of a plurality of memory cells.
Flash memory has been widely used as nonvolatile memory, and a larger capacity and a higher speed are demanded with the advancement of information and communications technology.
FIG. 27A shows a structure of a memory cell constituting a typical flash memory. Note that the memory cell is the minimum unit to store information of “0” or “1”.
As shown in FIG. 27A, a memory cell 10 is one type of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and includes an insulated floating gate 13, which is different from a typical MOSFET. A selection gate (word gate) 11 is formed above the floating gate 13, and the floating gate 13 and the selection gate 11 are insulated from each other with an inter-polysilicon dielectric film 12 interposed therebetween. The inter-polysilicon dielectric film 12 is called “inter-poly dielectric (IPD)” because the selection gate 11 and the floating gate 13 are generally made of polysilicon. Further, a gate dielectric film 14 is formed between the floating gate 13 and a silicon substrate, which is the same as a typical MOSFET. Further, inside the surface of the silicon substrate, electrodes serving as a source 16 and a drain 15 are formed with a gate placed therebetween, which is the same as a typical MOSFET.
As shown in FIG. 27B, the memory cell 10 performs storage operation by accumulating charge in the floating gate 13. Because the floating gate 13 is completely insulated from the surroundings, it has a structure (nonvolatile structure) where the accumulated charge does not escape from the gate even when the power is off. Thus, the memory cell 10 stores one bit of data depending on the presence or absence of charge by electrons in the floating gate 13.
The memory cell array according to related art where such memory cells are arranged in an array is disclosed in Japanese Unexamined Patent Application Publication No. 2000-49316. FIGS. 28A to 28C show the memory cell array according to related art disclosed therein.
As shown in FIGS. 28A to 28C, in a memory cell array 900 according to related art, a source region 903 and a drain region 904 are formed separately from each other in the surface area of a silicon substrate 901. The source region 903 is formed in a continuous pattern along the row direction and commonly connected between adjacent memory cells (common source line). On a channel region between the source region 903 and the drain region 904 of each cell transistor, a floating gate 906 is formed with a tunnel oxide film 905 interposed therebetween.
A control gate 908 is formed above the floating gate 906 with a dielectric film 907 interposed therebetween. The control gate 908 lies along the row direction and forms a word line.
On the above-described stacked gate structure, an interlayer dielectric film 909 is formed, and a bit line 910 and a source line 911 are formed on the interlayer dielectric film 909 along the column direction intersecting each word line (control gate) 908. The source line 911 is connected to the source region 903 via a through hole 913 in a source contact portion 912, and the bit line 910 is connected to the drain region 904 via a through hole 914.